Thanks for your suggestions, Peter.
Does the +Ve/-Ve Temp coefficients of "R" cancel perfectly that we don't need Trimming [To counter-act R variation over Temperature] to achieve +/1% accuracy? [Though How Trimming for Temperature variations is done is a question :( ]. This +/-1% accuracy should be met over 6-sigma [Process and Mismatch variation]. [
The Stigma of Six-Sigma :P]
Please see the Doc. attached for Figure taken from "A Temperature Compensated Fully Trimmable On-Chip IC Oscillator" by A. Olmos. The idea is similar.
i.e., Combine IPTAT+ICTAT=IREF and use Trimming to control IREF Vs Temp variations. And use only C [No Trmming for C , As It would call for huge area.]. Let the Temp Trimmed Current be IREF_T.
However the on-chip variation of C is counter-acted by changing the current "IREF_T" using another magnitude trimming. Let this current be IREF_TM
dV/dt=IREF_TM/C
1/dt=IREF_TM/[C*dV]=2*Frequency
Here dV is the Trimmed BandGap Voltage used for comparing the voltage across a Capacitor. This Capacitor is charged and discharged using IREF_TM during the alternate phases.
But, as you could see, this involves 2 levels of Trimming. I am curious to know If there would be a better method to realize Low-Frequency, Highly accurate OSC? [Better architecture with not-so-much of Trimming]
Thanks,
Packiaraj.V.