Hi, all,

I wrote the veriloga code for the comparator, but when I compiled this code, it reported:
"@cross(<<--? V(insin) - V(intri),0)",  Does anybody know where is the problem ?

My code is like this:

`include "constants.vams"
`include "disciplines.vams"

module comparator3(cout, intri, insin);

output cout;
input intri,insin;
electrical cout,intri,insin;
parameter real td = 1n,tr = 1n,tf = 1n;
 
analog begin
  @cross(V(insin) - V(intri),0)
     V(cout) <+ transition((V(insin) > V(intri)) ? 1:0,td,tr,tf);
end

endmodule


Please give me some instructions, thank you very much.

James

Hi, Ken,

Thank you so much. Now it is working. I would like to ask you another question about this model.

Now the V(cout) is 1V, but my supply is 2V, how can I program to make it reach  the full swing supply ?

or maybe, since my input signal intri and insin are not ideal signal, they all have a dc bias about 1V, how can I make my comparator output have a 1V dc , the it will reach 2V swing, I think.


Thank you very much
Best Regards
James

Thank you very much. It's working

Best Regards
James