Hey Guys,

I use the Pnoise analysis to verify the noise performance of a sample-hold block.
The SH uses a clock frequency of 200MHz. From the strobed Pnoise analysis I got the noise power density V^2/Hz
with I integrate up to 100Mhz to get the noise power.
The obtained value is close to the expected kT/C value.  :)
(thanks all for the help in the past on this topic!!)

The total input stage consists of two time-interleaved SH blocks.
each operating at 200MSs. Thus the total input bandwith is 200Mhz!

Over which bandwidth I have to integarte the  noise power density V^2/Hz
if I simulate both SH stages operating in a ping-pong (interleaved) fashion?  :-[
Still 100Mhz since each stage converts only 100Mhz?

Thanks

Frank,

I agree.

Only to be sure, that my approach is correct:
I use a 400Mhz clock (->beat fre=400MHz). The clock is feed into a divider
generating 2x200MHz clocks shifted by 180deg.

Since my beat frequency is 400Mhz, I have
to integrate over 200Mhz each SH output?
But each SH is only sampled at 200MHz?

What would be your approach to simulated such a circuit correctly
(an easy way to evaluate the noise perfromance of an time interleaved circuit?)

Thanks much
Friedel