Frank,
I agree.
Only to be sure, that my approach is correct:
I use a 400Mhz clock (->beat fre=400MHz). The clock is feed into a divider
generating 2x200MHz clocks shifted by 180deg.
Since my beat frequency is 400Mhz, I have
to integrate over 200Mhz each SH output?
But each SH is only sampled at 200MHz?
What would be your approach to simulated such a circuit correctly
(an easy way to evaluate the noise perfromance of an time interleaved circuit?)
Thanks much
Friedel