Naricissus,

  It is a little hard to follow your append. It appears that you designed a
polyphase filter for image rejection filter and there is less image rejection
than you expected.

Questions/Comments:

1) Is the filter an active or a passive filter?

2) Did you perform corner analysis on the filter design?
   What does simulation predict the filter rejection is across
   process?

3) What process are you using and did you perform LPE simulation?
   Device sizes change when printed on a wafer due to various effects:
   resistors are sensitive to overetch, ... Ideally, you would perform
   LPE, layout parameter extraction, and use the actual device sizes
   for simulation.

4) Did you perform RCX and include the layout parasitics in your
   simulation?
   RCX, parasitic RC extraction, extracts the layout parasitics

   NOTE: LPE is not the same as RCX, you need to account for both
             effects when designing

5) Do you have TEG data for the lot?
   If you skew the process based on the TEG data, are the results
   consistent with measurement?
   For example, if the the target for polysilicon sheet resistance is 20Ohms/sq
   and the measured value is 15Ohms/sq., scale the resistance values and
   re-simulate r_actual = (20/15)* r_target


                                                                        Best Regards,

                                                                           Sheldon