All,
I have designed a comparator, which is at the receiver path and the data frequency is 833 Mhz in 65 nm technology. One input of comparator is input data and the other input is Vref, reference voltage.The rise/fall mismatch has very stringent specs as the output of comparator is driving the latch of FIFO logic.
Also there is an margining test where Vref voltage is moved to see where the system is failing. This manifests that due to Vref moving, duty cycle of comparator output has worsened and which is violating the setup time of Receiver.

For this circuit, I ran the transient simulation for the rise/fall mismatch of the output of the comparator. Usually, one should simulate the offset of the comparator. But as such there was no spec for the offset. My dilemma was, even I simulate the offset across PVT, there is no way I can translate the offset to rise/fall mismatch.
Therefore, I didn't run the DC offset simulation.

However, for any device mismatch, I ran the statistical tool ( in which I can vary W,L, Vth, Cox) and calculated the rise/fall mismatch. The std. dev. of r/f mismatch standard normal distribution
is sigma and the +/- 3*sigma is within the specification.
My explanation for random offset was that by varying W,L, Vth, Cox whatever random offset is occurring will translate into r/f mismatch and hence in std. dev of r/f mismatch.
Am I doing right thing by not simulating my design for offset?

Thanks