I'm writing a model of a block designed by someone else. They have named one of the pins "I". I tried using "\I ", and this does not work. In the example below, I was able to successfully escape the "for" reserved word, but not "I".
Code:// Verilog-AMS
`include "constants.vams"
`include "disciplines.vams"
module block (\I , \for , x);
inout \I ; electrical \I ;
inout \for ; electrical \for ;
inout x; electrical x;
analog begin
I(\I ) <+ 1u;
I(\for ) <+ 1u;
I(x) <+ 1u;
end
endmodule
ncvlog -ams I-fails.vams
ncvlog: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.
I(\I ) <+ 1u;
|
ncvlog: *E,ILLPRI (I-fails.vams,12|4): illegal expression primary [5.2(AMSLRM)].
I(\for ) <+ 1u;
|
ncvlog: *E,ILLPRI (I-fails.vams,13|4): illegal expression primary [5.2(AMSLRM)].
I(x) <+ 1u;
|
ncvlog: *E,ILLPRI (I-fails.vams,14|4): illegal expression primary [5.2(AMSLRM)].
The following does work, but then I need to ask the designer to change the pin name and would prefer not to. Note that in this case, the "\for " is fine.
Code:`include "constants.vams"
`include "disciplines.vams"
module block (Ix , \for , x);
inout Ix ; electrical Ix ;
inout \for ; electrical \for ;
inout x; electrical x;
analog begin
I(Ix ) <+ 1u;
I(\for ) <+ 1u;
I(x) <+ 1u;
end
endmodule
Does anyone have any suggestions?