I am trying to use string type parameter in my veriloga model like below, the spectre simulator always complain syntax error. I have checked the spectre veriloga reference, it gives the example  same as mine. Is there anyone know why I cannot use this string parameter?

Thanks!


--------------------------------------------------------
module INV( in,out,vdd,gnd );
input in,vdd,gnd;
output out;
electrical in,out,vdd,gnd;

parameter real Cin_in1=9.342169858000004E-12 ;
parameter real Cout=1.7384E-14*2 ;
parameter string proc="typ";
......................................
-----------------------------------------------------------

Error found by spectre during AHDL read-in.
   "./INV.va", line 15: "parameter string <<--? proc ="typ";"
   "./INV.va", line 15: Error: syntax error

Thanks for reply. Actually cadence 6.0 supports the string parameter and it seems lower version does not.

//lili