Forum
Forum
Verilog-AMS
Analysis
Modeling
Design
Theory
Welcome, Guest. Please
Login
or
Register.
Please follow the Forum
guidelines
.
Jul 16
th
, 2024, 2:47pm
Home
Help
Search
Login
Register
PM to admin
The Designer's Guide Community Forum
›
Design
›
RF Design
› Jitter Issue
‹
Previous topic
|
Next topic
›
Pages: 1
Jitter Issue (Read 2360 times)
squirrelcn
New Member
Offline
Posts: 2
Santa clara
Jitter Issue
Oct 02
nd
, 2007, 9:34pm
I have a confusion of the "Jcc", "Jc" and "Jee".
It's the first time encounter "Jee" in the latest version cadence tool.
It is important to distinguish these three items.
Thanks for your hand!
Back to top
IP Logged
Stefan
Senior Member
Offline
Posts: 124
Re: Jitter Issue
Reply #1 -
Oct 3
rd
, 2007, 2:58am
I assume you read Ken's Paper on Jitter Measurements.The difference between cycle to cycle Jitter (Jcc), k-cycle jitter (Jc) and edge-to-edge jitter (Jee) is explained there in detail. I'm quite confused about Jee in cadence tools... Where did you find it ?
Back to top
IP Logged
squirrelcn
New Member
Offline
Posts: 2
Santa clara
Re: Jitter Issue
Reply #2 -
Oct 9
th
, 2007, 5:53pm
Thanks a lot!
I have find the answer following your guide
And I found the Jee in the 5.1.41 USR4 release of cadence!
Thanks again!
Back to top
IP Logged
Pages: 1
‹
Previous topic
|
Next topic
›
Forum Jump »
» 10 most recent Posts
» 10 most recent Topics
Design
»» RF Design
- Analog Design
- Mixed-Signal Design
- High-Speed I/O Design
- High-Power Design
- Mixed-Technology Design
Analog Verification
- Analog Functional Verification
- Analog Performance Verification
Measurements
- RF Measurements
- Phase Noise and Jitter Measurements
- Other Measurements
Modeling
- Semiconductor Devices
- Passive Devices
- Behavioral Models
- Transmission Lines and Other Distributed Devices
Design Languages
- Verilog-AMS
- VHDL-AMS
Simulators
- Circuit Simulators
- RF Simulators
- AMS Simulators
- Timing Simulators
- System Simulators
- Logic Simulators
Other CAD Tools
- Entry Tools
- Physical Verification, Extraction and Analysis
- Unmet Needs in Analog CAD
General
- Tech Talk
- News
- Comments and Suggestions
- Opportunities
« Home
‹ Board
The Designer's Guide Community Forum
» Powered by
YaBB 2.2.2
!
YaBB
© 2000-2008. All Rights Reserved.
Copyright 2002-2024
Designer’s Guide Consulting, Inc.
Designer’s Guide
® is a registered trademark of
Designer’s Guide Consulting, Inc.
All rights reserved.
Send comments or questions to
editor@designers-guide.org
. Consider
submitting
a paper or model.