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mattpace New Member Offline Posts: 4	Veriloga model of a current limted voltage source Oct 10^th, 2007, 6:53am Hi, I'm trying to model a current limited voltage source using veriloga. I thought it would be trivial, but it has turned out not to be. Has anyone done this please?
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Jess Chen

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Posts: 380
California Bay Area

Re: Veriloga model of a current limted voltage sou
Reply #1 - Oct 10^th, 2007, 8:20am

I have done this before with a resistance that draws current away from the output when the voltage exceeds a threshold. However, if I were to do it today, I would employ a trick that has served me well for the dual problem (a voltage limited current source). I placed a current feedback loop around a controlled voltage source and clamped the input to the controlled source. Within the limits of the input-referred clamp, the feedback loop forces the current to track the input. Once the input tries to exceed the clamp, the controlled voltage source limits and the output clamps at the desired voltage.

I am fairly sure you could do the same for a current limited voltage source. Place a voltage feedback loop around a controlled current source and limit the input to the controlled current source.

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Ken Kundert

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Silicon Valley

Re: Veriloga model of a current limted voltage sou
Reply #2 - Oct 10^th, 2007, 10:09am

You can also modify the ideal diode model given on the Verilog-AMS page to mimic a voltage source with current limiting. If you don't understand the ideal diode model, it is described in chapter 3, section 6.3 of The Designer's Guide to Verilog-AMS (http://www.designers-guide.org/Books/dg-vams/index.html).

-Ken

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mattpace

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Posts: 4

Re: Veriloga model of a current limted voltage sou
Reply #3 - Oct 11^th, 2007, 6:11am

Hi,
Thank you for your interest and responses.
Below is what I've come up with so far, it kinda works,
but it oscillates (using Sprectre).
I would have thought someone would have needed to
create a model of this, but I cannot find one.
Any feedback will be greatly appreciated !!!

`include "constants.vams"
`include "disciplines.vams"

module vdc_i_limited(vp, vn);
electrical vp, vn;

parameter real imax = 0.003; // current limit
parameter real vdc = 5.000; // V set
parameter real rsource = 1000;

real idc;
real vout;
real rload;

analog begin

@ (initial_step) begin
vout = vdc;
idc = I(vn,vp);
end

idc = I(vn, vp);

if (idc > 0.0) begin
rload = V(vp,vn)/I(vn,vp);
end

if ( idc < imax ) begin
vout = vdc;
end
else begin
//$strobe("idc = ", idc);
vout = rload*imax;
if (vout > 5.0) begin
vout = 5.0;
end
end

V(vp,vn) <+ slew(vout, 5e6);
end

endmodule

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Ken Kundert Global Moderator Offline Posts: 2386 Silicon Valley	Re: Veriloga model of a current limted voltage sou Reply #4 - Oct 11^th, 2007, 12:44pm You should start with the ideal diode model, it deals with the oscillation problem. Just change the zeros to the values you want and change the condition to switch at the right point. -Ken
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Peruzzi

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Posts: 71

Re: Veriloga model of a current limted voltage sou
Reply #5 - Apr 16^th, 2008, 4:37pm

This topic is a few months old, but I just saw it today when I needed to model a current-limited voltage source. My solution isn't original to me, I extracted it from http://www.beigebag.com/case_logical_9.htm "Logical Expressions - NO Smooth Switches and a Current Limited Voltage source".

But it's a nice solution, so here it is in easy to use form:

// Current limited voltage source
// imax
// -----
// vint ---| --> |------> vp
// | ----- |
// | |
// | \
// | / Rnil
// | | /| \
// |_____|/ |___|
// | |\ | va
// | | \|
// -
// / + \
// | |
// \ - /
// -
// |
// ----------------> vn
//
//

`include "disciplines.vams"
`include "constants.vams"

module vdc_i_limited(vp, vn);
electrical vp, vn;
electrical vint, va;
parameter real imax = 0.017; // current limit
parameter real vdd = 3.4; // V set
parameter real Rnil = 1e-9;

analog begin
V(vint,vn) <+ vdd;
I(vint,vp) <+ imax;
I(vp,va) <+ V(vp,va) / Rnil;

@(cross((V(va,vint) + I(va,vint)),0))
;

if((V(va,vint) + I(va,vint)) > 0)
V(va,vint) <+ 0;
else
I(va,vint) <+ 0;

end

endmodule

And a test circuit that sweeps a resistive load:

// Test vdc_i_limited model
//
// (n) ----------
// | |
// | |
// - |
// / + \ /
// vdc_i_limited | | \ Rsweep
// \ - / /
// - |
// | |
// | |
// (0) ----------
//

simulator lang=spectre

ahdl_include "vdc_i_limited.vams"

V1 (n 0) vdc_i_limited
Rsweep (n 0) resistor R = 400

doDCop dc print=yes
doDCswp dc start=400 stop=100 step=1 dev=Rsweep

The drawings got messed up, but you get the idea... Maybe attaching an ascii file...

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Peruzzi

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Posts: 71

Re: Veriloga model of a current limted voltage sou
Reply #6 - Apr 16^th, 2008, 4:46pm

I should also mention the ideal-diode code (comments added below) comes directly from Ken's Chapter 3, section 6.3.

This topic is a few months old, but I just saw it today when I needed to model a current-limited voltage source. My solution isn't original to me, I extracted it from http://www.beigebag.com/case_logical_9.htm "Logical Expressions - NO Smooth Switches and a Current Limited Voltage source".

But it's a nice solution, so here it is in easy to use form:

// Current limited voltage source
// imax
// -----
// vint ---| --> |------> vp
// | ----- |
// | |
// | \
// | / Rnil
// | | /| \
// |_____|/ |___|
// | |\ | va
// | | \|
// -
// / + \
// | |
// \ - /
// -
// |
// ----------------> vn
//
//

`include "disciplines.vams"
`include "constants.vams"

module vdc_i_limited(vp, vn);
electrical vp, vn;
electrical vint, va;
parameter real imax = 0.017; // current limit
parameter real vdd = 3.4; // V set
parameter real Rnil = 1e-9;

analog begin
V(vint,vn) <+ vdd;
I(vint,vp) <+ imax;
I(vp,va) <+ V(vp,va) / Rnil;

// Ideal Diode
@(cross((V(va,vint) + I(va,vint)),0))
;
if((V(va,vint) + I(va,vint)) > 0)
V(va,vint) <+ 0;
else
I(va,vint) <+ 0;
end
// End of ideal diode

endmodule

And a test circuit that sweeps a resistive load:

// Test vdc_i_limited model
//
// (n) ----------
// | |
// | |
// - |
// / + \ /
// vdc_i_limited | | \ Rsweep
// \ - / /
// - |
// | |
// | |
// (0) ----------
//

simulator lang=spectre

ahdl_include "vdc_i_limited.vams"

V1 (n 0) vdc_i_limited
Rsweep (n 0) resistor R = 400

doDCop dc print=yes
doDCswp dc start=400 stop=100 step=1 dev=Rsweep

The drawings got messed up, but you get the idea... Maybe attaching an ascii file...

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