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zhujun134

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how to reduce DC harmonic �in DSM?
Oct 10^th, 2007, 10:08pm

Hi,everyone,
� � � I am designing a fifth sigma-delta ADC,and when i implement the system in circuit in �cadence,i get a bad result.the psd of modulator's output inculdes large DC harmonic and small second harmonic! I have use the ideal opamp of verilog-a in modulator,but i get the same resulte.i have read a book,which indicate that the offset of modulator cause the DC harmonic!if so i can get perfect result using ideal opamp.
�would you give me some advice?thank you in advance!
PS:psd of modulator

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vivkr

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Re: how to reduce DC harmonic in DSM?
Reply #1 - Oct 11^th, 2007, 10:56pm

DC Harmonic ??? Perhaps you are interpreting the results from your modulator incorrectly.

If your bitstream is coded with values 1 and 0 and you pass it directly into an FFT, then you will
see a DC component simply because of this, and this will be large, around -6 dBFS, I would imagine.

More information from you might help someone help you.

Regards
Vivek

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zhujun134

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Re: how to reduce DC harmonic �in DSM?
Reply #2 - Oct 11^th, 2007, 11:56pm

hi,vivkr,

thank your reply!

I mean that the psd of modulator's output have large DC component,i think it is harmonic which is caused by DC leakage! and the bit-stream is coded with -1 and 1 ,so i think it is can not contain DC component!

I post my simulation result now,can you get it ?I have confused it a long time,but i can not resolve it!

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vivkr

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Re: how to reduce DC harmonic in DSM?
Reply #3 - Oct 12^th, 2007, 2:55am

Hi,

I would not have imagined that this level of offset would be a big problem. This could arise from various sources. Are you
using real switches for instance? Then, you would have some charge-injection and related offset, just to give one example.

I am also not sure how well you can simulate the DSM in Cadence in terms of accuracy etc. if you are worried about offsets.

Regards
Vivek

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zhujun134

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Re: how to reduce DC harmonic �in DSM?
Reply #4 - Oct 14^th, 2007, 10:12pm

hi,Vivek,
I use the full differential ciecuit in delta-sigma modultor,and i use the CMOS switches in DSM.and i have tried all accuracy in cadence,but i got the same result,i get this picture using moderate.
I have read the book which get the same result,but it use the lower voltage.this book is <LOW-POWER LOW-VOLTAGE SIGMA-DELTA MODULATORS IN NANOMETER CMOS>.if you are in interested in it ,i can send to you in email!

thank you!
regards

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vivkr Community Fellow Offline Posts: 780	Re: how to reduce DC harmonic in DSM? Reply #5 - Oct 15^th, 2007, 2:59am Hi Zhujun, I could only suggest that you try a simulation where both the switches and the opamp are ideal and see what you get. I think there should be no DC term there anymore. The DC offset probably comes from charge-injection for you. Regards Vivek
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zhujun134 Junior Member Offline Posts: 13	Re: how to reduce DC harmonic �in DSM? Reply #6 - Oct 15^th, 2007, 3:27am Hi,Vivek , Thanks!I will try once again as your suggestion.wish to get perfect result! Best regards! zhujun
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Berti

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Re: how to reduce DC harmonic in DSM?
Reply #7 - Oct 15^th, 2007, 4:52am

Hey Vivek,

I don't think that you will see offset due to charge-injection when simulating a fully-differential circuit.
Unless Zhujun models mismatch/offset in the simulation (e.g. montecarlo).

But I agree that -90dB is very low. I would recommend to double-check the way the digital bit-stream is processed.

Regards

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zhujun134

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Re: how to reduce DC harmonic �in DSM?
Reply #8 - Oct 15^th, 2007, 8:27am

Hi,Berti,
I don't know if i get offset due to charge-injection,but i really want to know charge-injection whether cause DC leakage!And i also agree with you,maybe, i have mistake when processing the bitstream.I have make the bitstream include 1 and -0.999,and i get similar result.
In the process,i get the bitstream from 50.5u to 3327.3u,which inculdes 8192 points.the clock frequncy is 2.5MHz.however,i do fft in cadence get the same psd as in MATLAB.i have tride to simulate longger time,getting more point ,but got the same result!I am confused.cab you give some advice?

regards!

zhujun

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vivkr

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Re: how to reduce DC harmonic in DSM?
Reply #9 - Oct 16^th, 2007, 1:22am

Hi Berti,

In principle, one ought not to see any offset in a fully diff circuit, but perhaps there is something in the real circuitry (as opposed
to ideal models) which might give some offset. One could then trace this back to the offending source to find out why this is happening.

Hi Zhujun,

I would also suggest you to check the transient outputs to make sure that your circuit has finished settling through the initial
transients, and the common-mode feedback circuit is also in steady-state condition.

Finally, I would say that if you are seeing a small offset, it might be also due to simulation or due to limited resolution of your
FFT. What you are seeing is very small and normally I would not worry about this DC term. But you can think about what it means
for your system.

Regards
Vivek

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