Hey,

Quote:


what do you mean with hybrid converter?
Because a cascaded modulator with high order first stage doesn't make sense.

I think the reasons that there are not so many cascaded modulators are:

• Many modulator are CT; and a cascaded CT modulator is difficult to design
• Single-loop (multi-bit) are much more tolerant to non-idealities (e.g. cap mismatch,
  OTA gain etc.) and are therefore preferred. Furthermore, deep-submicron technologies
  favour the design of comparators and DEM (used for multi-bit quantizers) rather than
  OTAs with high gain.

Regards

I think so....
...but on the other hand I also think that people often do such decisions according to "unscientific"
statements like "cascaded modulators suffer from noise-leakage" or "CT modulator consume less
power than DT". Maybe that's why CT single-loop is so popular..?..

In theory this might be true. But many CT modulators consume more power than DT modulators because
of wrong design decisions. Therefore depending on the specifications, a cascaded modulator might also
be good choice (and a good design won't suffer from noise leakage).

As you correctly wrote:
Quote:


Regards

Hey,

consider the design of a tri-level quantizer instead of a 1bit quantizer. As long you make sure that the offset of the amplifier is always transfered,
a tri-level quantizer is inherently linear but drastically reduces quantization noise compared to 1 bit.

Regards

Hi, vivkr.

I think multibit with DEM must be most high performance and main stream of DSM ADC.

But I'm considering adopting DSM to RF signal. So low resolution quantizer(feedback DAC)
is preferable.

Hi, Berti.

I plan to sample at about 1GHz.
So I think DT(SCF) modulator result in large power consumption.

I read old paper you teach about Tri-Level Delta-Sigma Modulation if I can get it.

Hi, Vivek.

Of course, I know CT-DSM you refer. This DSM is published at ISSCC 2006.
Features of this ADC are 4bit-3rd-Order-CT-DSM using NRZ-DAC with combination of Feedback and Feedforward.

I know 4bit quantizer is main stream in current DSM ADC.
The following paper's DSM ADC is also 4bit.
Richard Screier, et al.,"A 375mW Quadrature Bandpass DSM ADC with 90dB DR 8.5MHz BW at 44MHz", ISSCC 2006.

As I said in previous post, I still want to pursue any possibility of 1bit or less resolution quantizer.

I have interests in the approaches of following papers.
B.Putter, "A 5th-order CT/DT Multi-Mode DSM Modulator", ISSCC 2007.
Lucien J.Breems, et al., "A 56mW CT Quadrature Cascaded SDM Modulator with 77dB DR in a Near Zero-IF 20MHz Band", ISSCC 2007.

Hi Pancho,

Berti makes some important points. An SC-DSM would be a very hard undertaking from every front, and a
1-bit quantizer also would make life much harder.

Please note the various things that Mitteregger et al. have done. I will point out the key points I saw inthat
paper:

1. Use of CT DSM + mild input antialias filtering (not mentioned but there must be atleast some) implies
that system works in CT mode, that is no steps or any sharp transients on the input.

2. Since system is CT with no transients, it is possible to use pole-zero compensation in the opamp to
achieve wide bandwidth. No transients => step response not important, only steady-state response => bandwidth
only needs to be much much lower => lower noise, lower power.

3. Use of a latch in the DAC feedback path => comparator metastability not important. This in reality is a much
larger contributor to DAC jitter than just the clock jitter (see papers by Cherry & Snelgrove on this topic). The half-cycle
delay is compensated in the loop filter itself, and should partially reduce sensitivity to phase delay in the opamps (atleast
to my understanding but I may be wrong on this point).

You can use methods to shape mismatch in a multibit DAC. Of course, if you are constrained to use a 1-bit quantizer
due to system restrictions, then it is another story.

Maybe some SDM experts can add their comments here.

Regards
Vivek