Dear all,

I'm at the moment assessing some ring oscillator topologies (no prior experience). On the single-ended front, a
certain topology is rather popular. It basically uses a ring build up of 3-5 inverters, which are fed from the top (or bottom) by a current mirror. Just assume that this is a PMOS current mirror for the moment.

The frequeny control of the ring oscillator is than taken care of by an NMOS transistor below the steering part of this PMOS current mirror. The gate of this NMOS transistor is than controlled by the tune voltage (coming from the loop filter). The tune voltage thus sets the current and the current sets the oscillation frequency.

I now have following question: will this always lock in a PLL configuration? Because when the tune voltage is below the VT of the NMOS, the current mirror will be conducting very little current.

Of course, one could argue, that at this very small frequency, the PLL locking will drive the tune voltage up and up until the nominal frequency is reached.

I'm just wondering if anyone has some experience with this type of ring oscillator topology and can discuss this (potential) problem.

Kind Regards

Peter

suggestion - use a fully differential system there -

see the papaer by John Maneatis (IEEE JSSC - November 1996) for a good architecture for the VCO.