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Ultrasim problem (Read 6967 times)
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Ultrasim problem
Oct 19th, 2007, 8:37am
Hi - I'm new here. I'm a phd student in Edinburgh trying to use Ultrasim from within Cadence and I'm stuck on a problem:

I want to get different blocks to simulate with different levels of accuracy, so I've created a config view, set the properties for the blocks where I want to override the accuracy, clicked "allow usim_opt from HED" and simulated. I did this once, and then I changed my mind about what values I would want for the "sim mode" and "speed" properties of a block. So I went back to the hierarchy editor and changed it; I'd started with my block (called "StdDep") having sim_mode a and speed 5, and changed it to having sim_mode s and speed 1 - then I "saved" and "updated". However when I then re-netlist and run my change doesn't take effect - it still thinks my block has sim_mode a and speed 5 - it says this in the output log:

*ultrasim: .usim_opt sim_mode=a speed=5 #StdDep

Looking through the netlist folder I can see this in three places - in the files:


I've tried editing this in all those files so that the options are what I want them to be, and then running again with and without re-netlisting, but to no avail - the output log has the options as what they were before I changed my mind and where I edited gets overwritten in all those files.

Any idea's what I need to do? Any advice greatly appreciated.

Sim Bamford
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Silicon Valley
Re: Ultrasim problem
Reply #1 - Dec 18th, 2008, 7:45pm
Sorry you did not get a -timely- (sorry!!) response.
Ultrasim is a FastSpice simulator which can be used as a timing simulator, but I bet this category is not followed by many cadence folks who might be able to help you. In general your school should have a CAD representative who has been trained to capture your issue, and foward to the Cadence helpdesk to get you a timely response..

hoping this helps someone in the future..
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Mixed Signal Design Verification
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