kamath
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hai, i have coded a counter block ,could some one help me as i am not getting the required waveform at output:
// VerilogA for project, counter, veriloga
`include "constants.vams" `include "disciplines.vams"
module counter(incnt,cntclk,cntout,rst); input incnt,cntclk,rst; output cntout; electrical incnt,cntclk,rst,cntout; real step; parameter real vtrans=0.3; parameter real maxstep=15; parameter real minstep=0;
analog begin
@(cross(V(cntclk)-vtrans,1)) begin if((V(incnt)-vtrans)>0) step=step+1; else step=step-1; if(step>maxstep) step=maxstep; if(step<minstep) step=minstep; if(V(rst)>0) step=0; V(cntout)<+step; end end endmodule
please help me as i am new to verilog-ams. thank you
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