Hello,  I am trying to instantiate a Spectre voltage pulse source in my Verilog-A code like so:
vsource #( .type("pulse"), .val0( vss ), .val1( vdd ), .delay( tdel ), .rise( trise ), .fall( tfall ), .width( twidth ), .period( tperiod ) ) v1( a, b );

I get the error that "delay" is a reserved name of a simulator library function.

How can I instantiate this module without running into this delay error?  It seems I must pass the parameters this way, as just passing the values in order doesn't work.

Help!

Thank you!  I did some digging and found another workaround.  The reserved function 'delay' must be escaped, like so:

.\delay ( tdel )

Put a '\' before the word and a ' ' (space) after it.

Cheers!