I am trying to add some DFT features on chip to test 3rd order delta sigma adc/dac in codec application.
The ATE we use is not mixed signal ATE, it is digital; which makes me rely on the DFT/BIST added to thoroughly test the ADC/DAC.
My understanding is that,
Digital portion of the ADC and DAC are tested by standard digital dft techniques (scan/bist).
What are the ways to test analog portion on chip?
I see an issue in generation of analog stimuli on chip?
Also, what are the necessary and sufficient adc/dac parameters that needs to be measured (on chip) to qualify the production test?