Hi all,

i'm just looking for recommendations on 50 ohm output buffer design using 0.18 um CMOS. Its for on-wafer probing and the output signals are differential. Also the equipment is all 50 ohm. It is for a frequency range of 0.1 MHz to around 50 MHz.

thanks,
Aaron

What amplitude do you expect in 50ohm load ?

Buffer amplifier have to have current sink and source abilities which satisfy current>=amplitude/50ohm as well as voltage headroom.
If amplitude is large, we can't reduce MOS size and bias current.

But if amplitude is relative small and frequency is around 50MHz, the design specification of your buffer is to achieve low output impedance.
In this case, you can realize low impedance by source follower having local feedback without increasing bias current.

Hi loose-electron,

the proposed circuit sounds interesting. But what's about linearity? Do you think 14-15b linearity
can be achieved with such a structure.

However, does anybody have experience with buffer design for applications where very
high lineariy is required (14-15b)? Because this can't be achieved with a simple open-loop
circuit (e.g. source follower).

Regards

Berti wrote on Dec 6^th, 2007, 11:35pm:


Agreed - a source follower is not going to be able to get it done unless the signal is an extremely small part of the bias current - thus - really inefficient.

The linearity of the OTA structure has 2 parts to be considered -
-- linearity over what bandwidth?
-- how much gain is in the feedback loop?

lots of open loop gain feedback will get you to a good linearity, but only for low frequencies. As the OTA BW starts to play in, the linearity gets worse at high frequencies.

Now, what constitutes "low" and "high" frequency remains open for discussion. Can you get good enough linearity?
Need to put some numbers on it in terms of required linearity over what BW. I have used this tyoe of teshnique up to 100MHz in 0.25 CMOS, with reasonable results.