Hello,

I am trying to create a Standar Cell library in Cadence. To complete that, I am following a Standard Cell Tutorial of the Mississipi State University and Dallas Semiconductor. The tutorial tells that as soon as I build the layout, I need to do the DRC verification. After,. the next step is the extraction of the circuit. Then we have to extract the HSPICE Netlist, but we have had problems with that designing an inverter file. The log file has the following error:

ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'hspice cmos_sch schematic', for the
instance '+1' in cell 'inverter'. Either add one of these views to the library 'NCSU_Analog_Parts',
cell 'pmos4' or modify the view list to contain an existing view.

This is the liink where is the Standard Cells tutorial:
www.hpc.msstate.edu/mpl/education/cadence/standard_cell/files/standard_cell.ppt


I appreciate your help. Thanks