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jeffyan

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Re: PLL non-ideality
Reply #15 - Dec 15^th, 2007, 12:06am

aaron_do wrote on Dec 14^th, 2007, 6:04pm:

Hi all,

thanks for all the advice. I'll look into the phase domain model. Also the spike is a bit weird, so i guess i better investigate. I'm using detailed device models (Bsim3) and each block is designed down to the individual transistor sizes (it isn't in any standard library). In fact the change in capacitance i introduced is supposed to take place over a period of 1 us...

Anyway thanks for the help. I'll probably have to wait until after my holiday to do anything further.

happy holidays,
Aaron

HI
i calculated the third and fourth pole's position introduced by your LPF, it seems that they are very close, one is about 291KHz and the other is 272KHz, right? what is your phase margin of the Loop.
have a check.
good luck
jeff

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aaron_do Senior Fellow Offline Posts: 1398	Re: PLL non-ideality Reply #16 - Dec 15^th, 2007, 3:07am Hi Jeff, thanks. Actually I didn't design the PLL and i don't know how either. Also, the guy who did has gone on holiday. If it's simple could you tell me how to check? From the sound of it it seems like i would need the phase domain model... thanks, Aaron
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jeffyan

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Re: PLL non-ideality
Reply #17 - Dec 15^th, 2007, 11:54pm

aaron_do wrote on Dec 15^th, 2007, 3:07am:

Hi Jeff,

thanks. Actually I didn't design the PLL and i don't know how either. Also, the guy who did has gone on holiday. If it's simple could you tell me how to check? From the sound of it it seems like i would need the phase domain model...

thanks,
Aaron

hi,
it is hard to tell you how. but i can send you some papers about how to check the PLL loop stability in phase domain.
so could you tell me your mail address.
jeff

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aaron_do Senior Fellow Offline Posts: 1398	Re: PLL non-ideality Reply #18 - Dec 16^th, 2007, 3:55am Hi Jeff, thanks for the help. I managed to dig up some documents and i'll try it out as soon as possible. thanks, Aaron
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vivkr

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Re: PLL non-ideality
Reply #19 - Dec 16^th, 2007, 11:11pm

Hi Aaron,

You could also get a useful approximation if you just treat phase as it were a voltage and make a simple model
which will simulate quite fast. This will allow you do to the stability analysis very easily.

You can look up the chapter of PLLs in Razavi's textbook for an idea. Your PLL has a PFD+chargepump, a loop filter,
the VCO and the divider.

The loop filter stays as it is. The VCO can be replaced by an integration with TF = Kvco/s. The Kvco is the
voltage-frequency conversion gain. You can find this by doing a set of simulations where you vary the control
voltage and see the output frequency. The (1/s) comes because phase is the integral of frequency.

The PFD in this domain is just a subtractor, while the chargepump is a current source with value = the pullup/pulldown currents
in your chargepump.

The divider needs to be replaced with a corresponding phase delay. With this, you can do your analysis. As Jeff already pointed
out, you have 2 very close poles in the filter.

Good Luck and be careful with factors of (2*pi) while setting up various parameters.

Vivek

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wyyll

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Re: PLL non-ideality
Reply #20 - Dec 19^th, 2007, 10:52am

Hi Aaron,

If you look at the control voltage waveform after you add the capacitance to the LC tank, it suggests
that the PLL is locking, in response to a change in the trajectory of the tank. Consider that the period and
amplitude of the ringing changes with each successive cycle.

To see in your simulation if the loop has settled, plot out the voltage on the big damping capacitor. C11, in your
posted schematic. Has this voltage finished settling?

Having said this, I would again encourage you to get a phase domain model of some sort up and running,
as other before me have said.

I hope this helps.

Will

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