Designer’s Guide Community

aaron_do

Senior Fellow

Offline

Posts: 1398

PLL non-ideality
Dec 10^th, 2007, 7:31pm

Hi all,

I have a PLL which I am trying to simulate. The PLL has no problem locking after around 50 us with less than 1 mV variation in the control voltage. After 60 us, I introduced a change in the tank capacitance on the order fF. The PLL doesn't seem to have gone out of lock completely since the DC value of the control voltage remains the same. Unfortunately, there is a 2 mV periodic signal of 1 MHz on the control voltage. I'm not sure where this is coming from. Does anybody know about this?

thanks,
Aaron

Back to top

there is no energy in matter other than that received from the environment - Nikola Tesla

IP Logged

Berti Community Fellow Offline Posts: 356	Re: PLL non-ideality Reply #1 - Dec 10^th, 2007, 11:40pm Hi Aaron, What is the reference clock frequency? Regards
Back to top	IP Logged

aaron_do Senior Fellow Offline Posts: 1398	Re: PLL non-ideality Reply #2 - Dec 11^th, 2007, 3:33am Hi, the reference frequency is also 1 MHz. I expected the PLL to unlock and then slowly go back into lock... Aaron BTW the VCO frequency is about 2.4 GHz
Back to top	there is no energy in matter other than that received from the environment - Nikola Tesla IP Logged

vivkr Community Fellow Offline Posts: 780	Re: PLL non-ideality Reply #3 - Dec 11^th, 2007, 7:31am Hi Aaron, Berti's question is the answer in itself. You are seeing ripple on the control voltage at the same frequency with which you are updating your chargepump. Why is this unexpected for you? Regards Vivek
Back to top	IP Logged

aaron_do

Senior Fellow

Offline

Posts: 1398

Re: PLL non-ideality
Reply #4 - Dec 11^th, 2007, 5:43pm

Hi Vivek,

actually i'm not too familiar with PLL design, but the thing is the 1 MHz ripple is not there (at least not nearly as large) when the PLL locks for the first time. Only after I introduce the change in the tank capacitance. Also, the ripple does not seem to go away after an additional 40 us despite the fact that the PLL only took 50 us to lock in the first place.

cheers,
Aaron

Back to top

there is no energy in matter other than that received from the environment - Nikola Tesla

IP Logged

vivkr

Community Fellow

Offline

Posts: 780

Re: PLL non-ideality
Reply #5 - Dec 12^th, 2007, 10:59pm

Hi Aaron,

It has been quite a while since I did PLLs, but from what I recall, the ripple at reference frequency is typically determined
by the loop parameters of the PLL (the chargepump current and the passive elements, C1, C2 and R in the standard scheme).
You mention that you changed the filter cap by just a few fF. This should normally not cause a dramatic change.
I imagine that you have too little of C2 (the cap directly tied between the control voltage node and ground). All this
assuming that you are using one of the conventional chargepump PLL schemes.

Perhaps, you could post a snap of your filter and a couple of snaps of the ripple, and perhaps someone could help then.

Regards
Vivek

Back to top

IP Logged

aaron_do

Senior Fellow

Offline

Posts: 1398

Re: PLL non-ideality
Reply #6 - Dec 13^th, 2007, 7:24pm

Hi all,

here's a plot of the control voltage of the PLL, and the loop filter. The last cap on the loop filter was increased from 4p to 5p to see if there would be any change. Also, in this simulation, the PLL was simulated for 50 us before applying the change in tank capacitance of the VCO, so the control voltage is not quite as settled as it would be after 60 us. Any thoughts on why I am getting this ripple are welcome. Plots of the divider output and the reference frequency suggest that the PLL has not left the locked condition.

thanks,
Aaron

Back to top

there is no energy in matter other than that received from the environment - Nikola Tesla

IP Logged

jeffyan

Community Member

Offline

Posts: 47

Re: PLL non-ideality
Reply #7 - Dec 13^th, 2007, 9:34pm

aaron_do wrote on Dec 13^th, 2007, 7:24pm:

Hi all,

here's a plot of the control voltage of the PLL, and the loop filter. The last cap on the loop filter was increased from 4p to 5p to see if there would be any change. Also, in this simulation, the PLL was simulated for 50 us before applying the change in tank capacitance of the VCO, so the control voltage is not quite as settled as it would be after 60 us. Any thoughts on why I am getting this ripple are welcome. Plots of the divider output and the reference frequency suggest that the PLL has not left the locked condition.

http://i114.photobucket.com/albums/n280/aaron_do/ripple.jpg
http://i114.photobucket.com/albums/n280/aaron_do/rippleFilter.jpg

thanks,
Aaron

hi
i think it maybe caused by the fact that the freq of LC oscillaor changed too much, so that the loop need to re-settle.
and i think the loop will lock again after some time, is the large ringing lasting ?
good luck
jeff

Back to top

IP Logged

aaron_do Senior Fellow Offline Posts: 1398	Re: PLL non-ideality Reply #8 - Dec 13^th, 2007, 11:58pm Hi Jeff, thanks for the reply. The ringing is persisting and doesn't seem to be reducing (after an additional 40us...the initial lock time was only 50us). Furthermore, the PLL appears to be locked. The divider output is in phase with the reference clock.
Back to top	there is no energy in matter other than that received from the environment - Nikola Tesla IP Logged

Frank Wiedmann

Community Fellow

Offline

Posts: 678
Munich, Germany

Re: PLL non-ideality
Reply #9 - Dec 14^th, 2007, 12:28am

You might want to try different initial conditions for your original circuit (with 4 pF). Perhaps the good settling was just by chance. Another thing you could try is simulating your modified circuit (with 5 pF) with various initial conditions (but without changing the value during the simulation). You could also try some other capacitance values and see if you can find a pattern.

Back to top

IP Logged

aaron_do Senior Fellow Offline Posts: 1398	Re: PLL non-ideality Reply #10 - Dec 14^th, 2007, 12:32am thanks, I also have a feeling the good settling may have been by chance. Only thing is it takes about 15 hrs to simulate the PLL so its difficult to play with the values and find out what's wrong... Aaron
Back to top	there is no energy in matter other than that received from the environment - Nikola Tesla IP Logged

Frank Wiedmann Community Fellow Offline Posts: 678 Munich, Germany	Re: PLL non-ideality Reply #11 - Dec 14^th, 2007, 1:28am You might want to try using phase domain models to speed up simulation. See for example the pllLib from Cadence. The documentation is in Appendix G of the SpectreRF User Guide (http://sourcelink.cadence.com/docs/files/Release_Info/Docs/spectreRF/spectreRF6....).
Back to top	IP Logged

vivkr

Community Fellow

Offline

Posts: 780

Re: PLL non-ideality
Reply #12 - Dec 14^th, 2007, 2:37am

Dear Aaron,

I think Frank's suggestion is a good one. It is better to replace the various blocks with their equivalent phase-domain
models. This allows a much faster simulation.

Looking at your loop filter, I can see that it has 3 poles and a zero. This adds to the pole inherent in the VCO,
and the delay due to the divider.

Your ringing might also be owing to insuffcient damping in the loop. Perhaps you need to check the damping and
stability margins first. The phase domain model is a good starting point.

Regards
Vivek

Back to top

IP Logged

Eugene

Senior Member

Offline

Posts: 262

Re: PLL non-ideality
Reply #13 - Dec 14^th, 2007, 8:23am

I agree that a phase domain model check is a good idea. It would allow you to rule out small signal instability.

I also think it is interesting that the larger oscillation starts with a sharp spike. How detailed is your model? Does it include various modes of operation, like precharging the loop filter? Is it possible that the spike occurs because the PLL enters an unexpected mode of operation?

Back to top

IP Logged

aaron_do

Senior Fellow

Offline

Posts: 1398

Re: PLL non-ideality
Reply #14 - Dec 14^th, 2007, 6:04pm

Hi all,

thanks for all the advice. I'll look into the phase domain model. Also the spike is a bit weird, so i guess i better investigate. I'm using detailed device models (Bsim3) and each block is designed down to the individual transistor sizes (it isn't in any standard library). In fact the change in capacitance i introduced is supposed to take place over a period of 1 us...

Anyway thanks for the help. I'll probably have to wait until after my holiday to do anything further.

happy holidays,
Aaron

Back to top

there is no energy in matter other than that received from the environment - Nikola Tesla

IP Logged