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PLL frequency hop analysis (Read 2274 times)
keikei
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beijing
PLL frequency hop analysis
Dec 17th, 2007, 1:10am
 
Hi,
I was confused by some transient simulation results of two PLLs.
The two PLLs,  PLL 1 and PLL 2, of the same bandwidth, based on ring VCO. Initially they operate at frequency f1, and then both hop to f2.  To switch (f2-f1) in frequency, the control voltage of the VCO in PLL 1 varies ⊿V1, while that in PLL 2 is ⊿V2, and ⊿V1<⊿V2.
Someone says since the two have the same bandwidth, PLL 1 and PLL 2 will relock to f2 in the same time.  But it seems that the same bandwidth actually means the  same‘slew rate’of the VCO control voltage.  That is, if ⊿V1<⊿V2, then PLL 1 will relock faster than PLL 2.  
What is the problem in this analysis?
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Stefan
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Re: PLL frequency hop analysis
Reply #1 - Dec 17th, 2007, 4:45am
 
You're completely right.

Limited Bandwidth = Limited Slewrate

Just think of two identical systems with different initial states.
You wouldn't expect them to lock in the same time, but would expect them (well, first order only) to behave identical.
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buddypoor
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Re: PLL frequency hop analysis
Reply #2 - Dec 20th, 2007, 9:46am
 
Hello Keikei,

I am sorry but I really do not understand the problem.
As you describe both PLLs, they are identical, aren´t they ?
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LvW (buddypoor: In memory of the great late Buddy Rich)
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