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The Designer's Guide Community Forum › Design Languages › Verilog-AMS › How to build D-Latch in verilogA without hidden st
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How to build D-Latch in verilogA without hidden st (Read 2848 times)
AlexT
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How to build D-Latch in verilogA without hidden st
Dec 17th, 2007, 6:06am  
Hello Guys,
I have to build d-latch in verilogA without hidden states.
If anybody has advice, I will appreciate it very much.

Thanks a lot.
Alex.
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Ken Kundert
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Re: How to build D-Latch in verilogA without hidde
Reply #1 - Dec 17th, 2007, 9:18am  
See RF Models at http://www.designers-guide.org/VerilogAMS/.

-Ken
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seefree
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Re: How to build D-Latch in verilogA without hidde
Reply #2 - Dec 17th, 2007, 2:01pm  
You can define a flag signal when D and clk cross zero, and then, write the function of D-latch.
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