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The Designer's Guide Community Forum › Simulators › Circuit Simulators › Passing parameters hierarchically to verilog cell
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Passing parameters hierarchically to verilog cell (Read 1892 times)
rajdeep
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Passing parameters hierarchically to verilog cell
Dec 24th, 2007, 4:33am  
Hi all,

Does anyone know how to pass parameter values hierarchically into a verilog cell??

pPar seems to be useful for spectre/VerilogA types of views. It's not working for
verilog modules.

Rajdeep
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rajdeep
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Re: Passing parameters hierarchically to verilog c
Reply #1 - Dec 26th, 2007, 3:00am  
I forgot to mention. I'm using spectreVerilog and not AMS simulator.
Is it at all possible to do using spectreVerilog?
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