Hi Jim,

there are a lot of parameters you can simulate, however, you must discriminate between the linear model (with phase inputs/outputs) and the nonlinear model (with signal voltages).
a) linear: open loop response, closed loop BW, stability margin, loop damping
b) nonlinear: lock-in time/range, pull-in time/range, hold range, aquisition time, step response, PM/FM/AM demodulation capabilities resp. limits.

For example, I use VISSIM (from visual solutions) for PLL simulation of all these parameters on a block system basis. If you vary the incoming frequency during simulation it is possible to see the complete pull-in process.
Regards
Lutz (Germany)      

Hello Jim,

here some answers to your questions:

1a) You have achieved lock-in when the VCO frequency has reached the value of the signal frequency and there is a fixed phase relationship between both. This condition can be checked very easily in the xy-display mode (Lissajous-figures: circles resp. a 45 deg line)
1b) Pull-in time and pull-in range has to be verified by several simulation runs: When the PLL cannot lock-in within a limited time, than you are outside of the pull-in range. Try several frequency shifts of the incoming signal. In order to limit the number of simulations, it is good to calculate before a rough value for the maximum allowable frequency displacement.
2) The hold range must be simulated with the real model only. Start with nominal frequnecies in the locked condition and vary the signal frequnecy very slowly. When the PLL cannot maintain lock, you have reached the limit of the hold range.
3) What kind of model do you use ? A behaviour model (block system description) or models on a part basis (resistors, transistors etc.) ? Of course, the latter is more realistic.

Regards
Lutz

Hi Jim, here are some comments to your questions:

Q: I don't know what the xy-display mode is. The control voltage of VCO is usually used to observe whether it is locked.
A: The purpose of a PLL is to synchronize an incoming signal frequency with an internally produced VCO frequency. If you display the VCO frequency on a scope (resp. on a virtual scope after simulation) not vs. time but vs. the signal frequency you will get a perfect circle on the screen only if both frequencies are equal and the phase shift is 90 degrees. This is called a LISSAJOUS-Display. As these conditions apply to a PLL in a locked status and which has a multiplier as a phase detector, it is the best and most direct way to determine if the PLL has locked or not. By the way, which PD do you use ?  
 
Q: I think the way you mentioned in 1b) is try to find the pull-out range. And for a PFD PLL the pull-in range is inf, so I don't think it's necessary to simulate for the pull-in range.
A: Whether the pull-in range is finite or infinite depends on the loop filter (lag or PI); simulation makes sense only in the finite case.

Q: I do agree that the hold range should be verified by the real circuits, but there might be some issues such as at certain reference frequency, the PLL might be unlocked for a short periode and get locked very soon. For this situation, should this point be included in hold range simulation?
A: This case refers to the so called “lock-range” and has nothing to do with the hold range.
The hold range applies to a slow and continuous shift in frequency as described in my reply before.

Q: I use the behaviour model, so I doubt whether the model could describe the circuits accurately. I don't know how to model the pll with resistors and transistors. Could you give me some hints?
A: It is best to see a scetch of your model including PD and loop filter. If I have your e-mail address I even could send you some additional information (e.g. my block model and some simulation results) .
Regards
Lutz