Hi,
You can create a VerilogAMS view of the diffamp.
This diffamp would have the same interface as the spice level design you have.
It is just a wrapper. Then instantiate the diffamp as a subckt. It is possible to
use a spice/spectre subcircuit from a verilogAMS model. Then create a symbol of it and use it with
the DAC.
There are some issues though which I donot know offhand..
1. If you want to use spectre as the simulator, you have to use VerilogA instead of VerilogAMS. I hope
one can instantiate a spctre/spice subckt in a verilogA module also. I have never tried the latter though/
2. How will you include the spice netlist of diffamp?? I once simulated a design, partly in spectre and VerilogAMS, but I used command line interface, i.e. ncsim -ams. I included the subckt definition in a file named hdl.var as below:
Quote:define MODELPATH ldotest/SpectreFiles/<netlist.scs>
There must be some way to tell the simualtor from where pick up this subckt definition using some option
of ADE, or may be it can be included in the verilogA/MS file iteself using include directive!! Not sure though.
Hope that helps.
Rajdeep