SOC has PLL ,transmitter,receiver and some digital blocks. The placement is shown in the attached document.
A PLL (working as a freq synthesizer) gives clock to T1-4(which are blocks of transmitter) and R1-4 (which are blocks of receiver). At the receiver end we are getting a problem –bit errors are coming b/w R1,R2,R3,R4 i.e some delay is happening and coz of tht noise n jitter is happening post fab.What can be the possible solutions for this problem….is adding buffers between the paths a solution? Or can anyone suggest some possible solutions from layout point of view….

Hi

b/w means between.
The problem is that we have a PLL on a chip which also has a transmitter and receiver(many sub blocks inside Transmitter n receiver:T1-4,R1-4)
This PLL gives clock to the Tx and Rx. On Silicon, we are facing problem at the receiver end: noise and jitter. We have observed that there is a problem with the clock that is coming from PLL to Rx. The clock has a skew at the receiver end. Different blocks of receiver are getting clock with some skew and hence we are getting bit errors. I am looking for a solution to this problem from both layout and design angle.

Adding buffers will increase jitter due to power-supply noise injection.  But
you might be able to deal with your skew problem by path matching (e.g
identical buffer #, size, load) on each path.  Lots of SerDes use a single pll,
but put local phase-interpolators on the clock-path or deskewing-buffers on
the data-path.  I hope I'm understanding your question correctly, and not suggesting
the obvious!