With assignments in Verilog there are several different things going on at once. In particular ...
1. The time when the right-hand side is evaluated.
2. The time when the assignment to the left-hand side occurs.
3. Whether assignment includes delay.
4. Whether the delay blocks execution.
Assignments using the "=" operator are considered blocking assignments because if they include delays they will block execution during the delay. In this case, the order of evaluation is ...
1. evaluate the right-hand side.
2. block execution for the length of the delay.
3. assign the value to the left-hand side.
4. execute the next statement.
Assignments using the "<=" operator are considered non-blocking assignments because they do not block execution even if they include delays. In this case, the order of evaluation is ...
1. evaluate the right-hand side.
2. execute the next statement.
3. continue execution while waiting for the length of the delay.
4. assign the value to the left hand side.
Analog assignments never block. So the order of evaluation is ...
1. evaluate the right-hand side
2. assign value to the left-hand side
3. execute the next statement.
So the point is analog statements are all non-blocking. But this does not mean that analog assignments act in the same way that traditional verilog non-blocking assignments act. Traditional verilog non-blocking assignments have behavior in addition to the fact that they do not block execution that is different from the behavior of analog assignments.
The behavior of analog assignments is the same as the behavior of assignments in traditional programming languages. It is also the same as simple verilog assignments that contain no delay.
For example,
Code:analog begin
a = b;
c = a;
end
would end up with c getting the value of b, as you say.
-Ken