The Designer's Guide Community
Welcome, Guest. Please Login or Register. Please follow the Forum guidelines.
Jun 24th, 2024, 8:35pm
Pages: 1
Send Topic Print
How to improve op's noise performance (Read 825 times)
Community Member

Posts: 66

How to improve op's noise performance
Jan 10th, 2008, 2:02am
For a folded-cascod op, I want to improve its noise performance. In generally, increase W*L and W/L can decrease flick noise and thermal noise, however there is no enough layout area margin.

In theory, increasing the current can improve it, however the simulation shows the noise becomes a little larger with the current increase with UMC model. It is strange.

Is there any other method to improve op's noise performance without increasing area obviously? Thanks.
Back to top
View Profile   IP Logged
Community Fellow

Posts: 493

Re: How to improve op's noise performance
Reply #1 - Jan 10th, 2008, 8:06am
Hi Trashbox,

Concerning flicker I guess the only way out is the one you mentioned. Concerning thermal, you can play around with the input gm1 by either putting more tail current or increase W/L as you pointed out. However, from the output integrated noise this will not be useful, since the BW under which you have to integrate that noise is proportional to the input gm (and inversely proportional to the compensation capacitor. Therefore the effect of gm gets canceled out.
Bottom line, no matter what you do with your input gm, the one setting the output integrated noise level will be the compensation capacitor (the larger the better for reducing noise). This is true assuming the input gm is much larger than the gm of the folded cascode circuit, which is valid for most of the cases.
The output integrated thermal noise (noise power) will result equal to (4/3)KT/Co, where Co is the compensation cap.

Reducing noise is always about increasing power or area.
Hope this helps

Back to top

Keep it simple
View Profile   IP Logged
Community Fellow

Posts: 780

Re: How to improve op's noise performance
Reply #2 - Jan 11th, 2008, 4:02am

A few more points in addition to the excellent ones from Tosei:

1/f noise may also be easily modulated out of band with chopping or correlated double sampling (CDS) at the cost of additional complexity and in
case of CDS, extra noise and power consumption.

An important point which is often overlooked is the possibility of actually improving the noise performance of your amplifier itself. The (4/3)kT/Co
limit is the limit on the total noise power in the entire relevant bandwidth of the opamp. However, this assumes

(a) that the noise comes only from the input pair. An assumption which is unfortunately not true. The other transistors will also add noise,
and depending on the necessary swing and the quality of design, the additional noise from these devices might become significant. In a folded
cascode amp, there are noise contributions from the P and N current mirrors in addition to the input pair, if we ignore the cascode noise contribution.
The gm of these mirror devices must be significantly smaller than the gm of the input pair to suppress their noise. In a poorly optimized design, this
is not the case. You should try to quantify the total noise power in band vs. the noise power due to the input pair as a quality factor. A good value
to aim for is to get the total noise power of the amp to be between 20% - 30% greater than the contribution of the input pair. If you can achieve this
goal, then you can be happy.

(b) Remember that although the total noise contribution is limited by C0, the noise floor will be reduced with higher gm. This helps if you are
aiming for a continuous-time application where the noise is of interest in a small bandwidth only, or where you have some stages later on which
limit the bandwidth.

(c) Finally, you should seriously consider using another opamp topology. Folded cascode opamps are the noisiest from a simple analysis
perspective because you have 4 additional transistors (apart from the input pair) adding their noise.

Back to top
View Profile   IP Logged
Pages: 1
Send Topic Print
Copyright 2002-2024 Designer’s Guide Consulting, Inc. Designer’s Guide® is a registered trademark of Designer’s Guide Consulting, Inc. All rights reserved. Send comments or questions to Consider submitting a paper or model.