Hi,

I am looking for ESD protection structures for Power Amplifier. Any references (books, papers) would be helpful.

Regards,
Faisal

Why dont you simulate  an ESD event on the PA and see what happens?

Suggest that you be fussy about including metal path RLC elements, ESD event will briefly have over 1-2 amps of current flowing.

probably a good starting point.

-- Jerry

Geoffrey,
You are correct, without proper models simulating the ESD event is very difficult.  Not only do you need a proper snapback model but it must also account for other third-order effects such as thermal heating of diffusion, contacts and metal, as well as have accurate avalanche models if you want to capture the proper snapback trigger level.  No foundary I know offers this unless you work for TI, Freescale, or IBM and even then they keep most of their models locked up tight not to mention that the models are very layout specific so that if you have a layout remotely different from what was modeled, forget about the accuracy.  Some smaller foundaries do play with ESD models but I have rarely seen any that were very useful or accurate for general simulation.  There are new papers every year on ESD simulation models and nothing I have seen has become widely adopted or withstood the test of time.  (there were 6 papers proposing new modeling techniques just this past year at ESD/EOS symposium )

ESD events can be simulated relatively accurately if you are using an active BigFET design and the current densities per unit um are within model ranges of normal device operation...but this is an exception and not very good for an RF PA.

In the case of an RF PA, ESD can be a pain.  Using discrete ESD structures cost area and performance, so it is generally avoided.  Drain ballasting (in this case by using silicide blocking) as suggested by Faisal has a significant power impact as menioned so we always try to avoid it.  (though proper ballasting can be achieved without a power or headroom hit using specific layout techniques, but again only if your design can afford the layout approach which it may not).

Essentially, there is no one good approach for RF PA's, I have worked on 7 different PA's for 3 different applications and have used an almost entirely different approach for each one.  In somecases, depending on the process and the nature of the design, we had to take explicit steps to provide ESD protection, and in others, did not need to do anything at all because the PA process and layout itself was sufficient to protect it.

Faisal,
You need to know what the risk is for your PA in terms of snapback triggering, and thermal runaway.  The design itself maybe sufficient.  Since you are unsure, first go to your foundary and see if they can answer the question regarding the weakness to snapback of your driver device.  If they have no idea, you need to get a few sample devices of your PA (does not have to be your PA design but silicon using the same device in a similar layout) and test them using a TLP (transmmission line pulse) machine to study the health of the process.
Form that point you will need to decide what best to do for your ESD.

-Stephen

loose-electron wrote on Mar 14^th, 2008, 7:37pm:


This assumes the protection network is made up of diodes, and no GGNMOS or such, doesn't it?  OK, in this case, I believe you can simulate it.

Thank you Jerry, Stephen and Geoffrey for your answers.

With the transistor models available from the foundry, it is not a possibility to simulate ESD events in Spectre. I would try with the another layout style, but will have to check with the foundry ESD experts on this subject.

Kind Regards,
Faisal Mateen.