hi All,

If you happen to have access to Schreier's sigma delta book "Understanding Delta-Sigma data converters" (IEEE Press) you might be able to help me out. In Chapter 9 there are several practical examples. In particular the first example corresponds to a fifth-order single-bit noise shaping loop(switched cap feed-forward topology).

The way the design process is described is pretty clear. However, there is a quick question I have concerning the summing stage (prior to the comparator) this example shows. On page 305, a summary tables shows the coefficients and capacitor ratios used in the design for this modulator. Most of these ratios (summing coefficients) are higher than one for the summing stage. However, as it can be seen on the corresponding behavioral schematic on page 309, the summing stage is a passive one. So, how can the design implement higher than one cap ratios with a passive summing stage? Am I missing something?

Many thanks
Tosei

Hi,

That´s make total sense. I guess then the approach shown in the book is only valid for single bit quantizers. Otherwise such gain loss could not be absorbed by the quantizer.

Thank for your help
Tosei

I guess that for a multi-bit approach where coefficients are still less than 1, a passive approach might be an option. Certainly it is not in case there are coefficients higher than 1.

Tosei