Hi, I have encountered problem to elaborate my project.

To start with, I have 3 VHDL blocks in my project, namely DPWM,PID_compensator, and ADC. i have successfully connected DPWM and PID_compensator together and compile, elaborate them without any errors. So I assume both of the blocks are ok and ready to simulate. The problem arise in the ADC block. I think the problem arise because I use VHDL in describing it rather than verilog-ams or vhdl-ams. The following error message appears:

ncelab: *E,CFMPTC (../hc/zzz_adc/schematic/verilog.vams,17|51): VHDL port ADC_DELAY_CELL_3.OUTPUT (../hc/adc_delay_cell_3/entity/vhdl.vhd: line 10, position 16) type is not compatible with Verilog.

the correspong VHDL port is :
Port ( vdd : in  real range 0.0 to 5.0;
          input : in  STD_LOGIC;
          reset : in  STD_LOGIC;
          output : out  STD_LOGIC);
the error message point out that the output port is incompatible with verilog. But I wonder is it due to input port vdd ? Does type real supported in this case?

the connect module I use is copied from the one used in quick start tutorial. I just copy the whole connect lib module over and use it. the connect rule I use is ConnRule_25V_mid.

Thanks a lot