Hi all,


i've been researching low-power receiver design for a few years now, but one thing has always bugged me. Commercial receivers use a lot more current than those reported in literature (academic research) despite comparable performance.

Some things i've noticed are that most of the designs in literature concerning receiver design do not include an ADC (although some do), but commercial designs tend to report the current consumption of the whole receiver including baseband and DSP. Commercial designs also seem to include calibration for just about every component, while those in literature tend to live with what they get in terms of LO amplitude, and sometimes even channel select filter center frequency etc.

So i'm hoping for some advice from experienced designers. Where does all the power go? Is it simply to improve the robustness of the circuits? If this is the case, companies developing these chips (TI, freescale...) follow literature when choosing their designs and simply make them more robust?


thanks,
Aaron

Hi Aaron,

I think an other point is that published designs often only serve a research and prototyping purpose.
As Stefan said, because of the long development time and high costs for a new transceiver, the industry often
prefers to rely on older designs, which have probably worse performance, but are robust and
well characterized.

Regards

There are so many journals and so many papers published every month. It would be unrealistic if not unfair to expect that they are all
equally good. In this I have to agree with Jerry that often, the authors who are trying to present a new idea may tend to focus
too keenly on the brighter aspects of their work while downplaying the role of support blocks, yield etc. To a certain extent, this
is fair. After all, if you are really presenting an idea which is revolutionary and may be of great use in the future, perhaps you can
be forgiven for not getting all the things quite perfect. To what extent is a matter of debate.

I would also disagree with some others who say that the commercial devices consume more power because they tend to favor older,
more trusted schemes. I would say that the most important factor is their need to guarantee reliable operation across various conditions
(not just at room temperature for 5 out of 50 chips) and the need to provide a large number of support blocks. Innovation in industry is
as high as in academia provided you compare good companies to good univs and vice versa.

Perhaps the best way to get around the problem is to look at papers which are really classics, or if you need more current material (it
takes a few years for a paper to get into the classics list at the least), then rely on your experience to weed out the ones which have
got the right stuff from those which don't.

Looking at the JSSC classics list, one is struck not only by the fact that the bestsellers seem to come from a handful of companies/universities
(Philips/U.C.Berkeley/IBM etc.), but also by the impact most of the papers have had. Perhaps, not all good ones have made it, but that
is usually rare. One can also see which ones will come on the list in the next few years (Bult & Geelen's paper on gain boosting for instance).

So I suppose we all need to use our own judgement in the end.

Vivek