Hello,

I am interested in using Verilog to model some blocks in a PLL in order to do a closed loop PLL simulation.  I am interested in the PLL settling, in particular the effect of cycle slipping.  I would like to use Verilog to model the VCO and frequency divider.  I plan on using the transistor level PFD, CP and loop filter.  My questions are:

-Can a simulation be done in Spectre using the Analog Environment with transistor level schematics and Verilog code?
-Is Verilog AMS the best tool to use, or are Verilog-A/VHDL more appropriate for the VCO/frequency divider respectively?
-Does the Verilog code need to be imported into Cadence?  If so, how is that done?
-Is there existing documentation or papers that explain this type of simulation?

Thanks for your time.

Regards,
Tim

Hello Stefan,

Thank  you for replying, your answers help a lot.  One follow up question:

-Do I need to select the AMS plug-in in the hierarchy editor in order to simulate with Verilog AMS code?

Thanks again.

Tim