Berti wrote on Feb 4th, 2008, 11:57pm:Thank you Jerry for this overview.
Concering reliability: Is that correct that I only need to make sure that vds, vgd and vgs are smaller than the maximum rated supply voltage? For voltages
to substrate (vsb, vdb, vgb) I have to consider the junction breakdown voltages? (Assuming that there will be a channel present when the gate
voltage is high for NMOS, and low for PMOS, respectively.
Regards
Hi Bert,
Would you really consider vgb?? If vgb is high, then you have the channel which screens the bulk from the gate. I would expect
that as long as you have vgs, vgd (gate oxide reliability) and vsb,vdb (reverse breakdown of diodes) in safe range, you should be ok.
Otherwise, it would be very difficult to design cells such as chargepumps (not the ones from PLLs), or bootstrapped switches.
Regards
Vivek