Several approaches:

A driver at the low voltage tranfers a signal to a higher voltage through a capacitor. The higher voltage circuit is all done with PMOS and the PMOS well is tied to the higher voltage. The large offset voltage appears only across the capacitior.

Or possibly:

An NMOS current source provides a current through a resistor to a PMOS device connected as a diode to the top power rail. Most of the voltage appears across the resistor. (Need to provode diode limiters across the Vds of the NMOS so it never goes ovevoltage when starting up)

Or possibly:

An "accordian approach" - where multiple transistor are used in series to spread the large voltage across multiple transistors, with fractional increases in voltage across each transistor.

Or possibly:

A transformer approach, useful more in the integrated RF world, drive the primary and the seconday can be connected to pretty much anything. All the voltage appears accross the transformer and the signal is transferred magnetically.

On all methods, you need to be very fussy about power cycling on/off and what the voltage of all your gates are at with respect to your bulk voltage. Mess that up and you fry transistors.

Dpending on you application one of these should work for you. All of them have been used with success. The capacitive coupling methd is easiest to design generally, but it is going to depend on the signal that you are level shifting.

Berti wrote on Feb 4^th, 2008, 11:57pm:


Hi Bert,

Would you really consider vgb?? If vgb is high, then you have the channel which screens the bulk from the gate. I would expect
that as long as you have vgs, vgd (gate oxide reliability) and vsb,vdb (reverse breakdown of diodes) in safe range, you should be ok.
Otherwise, it would be very difficult to design cells such as chargepumps (not the ones from PLLs), or bootstrapped switches.

Regards
Vivek

you really have to be very fussy when doing things outside the box with high voltage.

back biased bulk diodes that you normally just ignore can get into a zener state, snapback efects, other nasties, so you really need to take a very close look at the relative potential of everything, and be aware that you can be bitten by things not in the transistor model.

XY-oriented wrote on May 1^st, 2008, 6:10am:


This is connecting multiple transistors drain to source ina chain, and dividing the voltage drops across multiple transistors so that there are no voltage violtions on one transistor. If you go there you need to be real fussy on power cycling on/off and any siturations you might run into where the voltage is not evenly distributed.

jerry