Hi,
If the paper is:"A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and
Clock Recovery", the title says all:they do the synchronization with DSP, look at the reference [5]:K. Mueller, M. Muller “Timing Recovery in Digital Synchronous DataReceivers” IEEE Trans. on Communications, pp. 516-531, May, 1976. This kind of algorithm if I remember correctly it's based in adaptative convergence, the speed of convergence usually is dependant if you use NDA(Non-Data Aided),DA(Data Aided-->syncronization data sent with the signal and known) or DD(Decision Directed, it decides what symbol it received and adjust following this decision and so on).
Hope it helps,