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dandelion Community Member Offline Posts: 98	The 80umx80um PAD size for COB package Jan 29^th, 2008, 2:21am hi, My project used 0.5um CMOS process and the design rule gives 90umx90um PAD size recommendations. For area considerations, my pad is decreased to 80Umx80um and the chip will be COB(Chip on board) packaged. Would any one pls. give me advcie if it have any risks? Thanks
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Berti Community Fellow Offline Posts: 356	Re: The 80umx80um PAD size for COB package Reply #1 - Jan 29^th, 2008, 10:33pm I think the pad size is usually limited by packaging (bonder, probe etc.) and not by the technology. Regards
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ywguo Community Fellow Offline Posts: 943 Shanghai, PRC	Re: The 80umx80um PAD size for COB package Reply #2 - Jan 31^st, 2008, 9:21pm Hi Dandelion, 80um X 80um is enough for my package house. However, it is a good practice to confirm with your package house before tape out. Good luck Yawei
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loose-electron Senior Fellow Offline Best Design Tool = Capable Designers Posts: 1638 San Diego California	Re: The 80umx80um PAD size for COB package Reply #3 - Feb 4^th, 2008, 12:58pm Check with whoever is doing bond wires to the pads what their minimum pad size is acceptable. Generally (but not always) thats the packaging house.
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Paul Community Fellow Offline Posts: 351 Switzerland	Re: The 80umx80um PAD size for COB package Reply #4 - Feb 26^th, 2008, 12:53pm Hi, When talking to your packaging subcontractor, also check for pitch. During PhD, I noticed the constraints of some suppliers were not that much about pad area (80x80um2 sounds comfortable), but more about pad pitch. Paul
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ywguo

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Posts: 943
Shanghai, PRC

Re: The 80umx80um PAD size for COB package
Reply #5 - Mar 5^th, 2008, 5:50pm

Hi Guys,

It was a total failure that my chip was COB packaged for the first time. The package house ensured that they can do COB even if the pad pitch is as small as 35um. So we used stagger I/O to put more pads on the chip. Then we found most chips were short or open after they are COB packaged.

It is a little lucky that the COB package successed for the second time. �I chose inline I/O, and make the pad pitch is about 120um. 3 chips are COB packaged in another package house. One was short between power and ground. I didn't check it. The other two works fine.

I found the requirements are so different for each package house. And they use different material, like the glue covering the chip. Sometimes they don't cover the chip. �Would you please introduce any literature, application notes, books on COB technique? Especially the material's effect on the electrical performance, the relative PCB layout, etc.

Best regards,
Yawei

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