Hello,

I am having some trouble running a very basic simulation using spectreVerilog through the hierarchy editor/analog environment.  The testbench consists of 2 logic gates, one using a Verilog-XL view and one using a transistor level view.  I can successfully run a DC simulation and I can see the resulting node voltages are correct.  If I try to run a transient simulation, I see the following error in the spectre.out window:  'Error found by spectre during initialization.  Error while starting attached simulator.'  Also, my understanding is that a second verilog.log window should pop up when running the transient simulation, but I do not see this window (it does not pop up after a DC simulation either).  I have verified that I have selected spectreVerilog as the simulator, and that the proper libraries and design variables are set correctly.  I also verified that the paths to verilog.vmx and verilog.exe are set correctly.  Any help with this issue to get a transient simulation started is greatly appreciated.  Thanks in advance.

Regards,
Tim