Hi everybody,
I was trying to simulate a PLL circuit using SpectreVerilog. The digital block is a verilog model that reads in an array of 5bit data from a file. This block outputs the 5bit data at the rising edge of an input clock. Essentially I want the block to act like a shift register (and the 5bit data is used to control my frequency divider in the PLL). What I found was the 5bit output changes state not only on the rising edge of the input clock, occasionally, it also changes state on the falling edges. It appears that these falling edge events only happen if the  input clock has a slow edge (say fall time of 300ps). Does anyone know what's causing these miss triggered events?

The verilog model is a simple $readmemb plus an always @ (posedge clk).  
I also tried with different interface element a2d parameters, but made no difference.

Please help.
Thank you!
sofiap