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Leila

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Comparator's linearity for SAR ADC
Feb 14^th, 2008, 2:57pm

Hi,
My intention is to design a comparator, I choose the NMOS Diff amplifier with PMOS load and used the resistor CMFB, for my ADC precision I need to get a gain about 32. I sweep the input common mode with the range between 300mV and 600mV, then I see 25% variation in circuit gain for this sweep in input.

I force all transistor to work in subthreshold, I know the short channel effect makes to reduce the gds, I tried to remove the change in the current tail now I get the 5% change in gm compare with 18%. But still could not see constant gain. Sounds that I am not in the right way.
Is there any way to make the gain for different input common mode approximately constant?

Or I should not worry about the linearity and if in the worse-case I get enough gain and for the rest more gain that will be fine for my ADC?

Please Advice,
Thanks

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vivkr Community Fellow Offline Posts: 780	Re: Comparator's linearity for SAR ADC Reply #1 - Feb 14^th, 2008, 11:00pm Hi, I would just try to make sure that the comparator has enough gain in the entire range of interest. The comparator should have enough gain to amplify a relatively small signal into fullscale logic levels (when a latch is included) And this should be done within the available time. Regards Vivek
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fonseca.ha Junior Member Offline Posts: 28 UK	Re: Comparator's linearity for SAR ADC Reply #2 - Feb 15^th, 2008, 5:18am Hi If the input common mode can be as small as 300mV it seems that an NMOS differential pair may not be the best solution. I think that the current source that bias the differential pair may be without headroom. what is the value of your sypply? can you consider using a PMOS diff pair? Regards, Humberto
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vivkr

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Re: Comparator's linearity for SAR ADC
Reply #3 - Feb 15^th, 2008, 6:22am

fonseca.ha wrote on Feb 15^th, 2008, 5:18am:

Hi
If the input common mode can be as small as 300mV it seems that an NMOS differential pair may not be the best solution. I think that the current source that bias the differential pair may be without headroom. what is the value of your sypply? can you consider using a PMOS diff pair?
Regards,
Humberto

Or you can use a capacitively coupled comparator. The input common mode levels are freely chosen by you to optimize performance. The input common mode variation
goes out of the picture completely. So your original problem does not exist here anymore.

Vivek

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