Min,

 Basically, there are only two devices in the signal path so there
is not a lot that can be done to improve the phase margin. Could
you provide any information about the bias and the device sizes?
Those are really the only variables available.

                                                          Best Regards,

                                                             Sheldon

I think 55deg phase margin is at the (very) lower end for a SC-circuit. Such a phase-margin might be okay for a continuous-time circuit (or in a PLL loop).
But in a SC-circuit the input is basically a step and with only 55deg phase margin you will see ringing at the output, which is far from nice settling.

- To improve phase margin you can shift your dominant pole to lower frequencies as proposed by safwatonline.
- Or (the solution I would choose), redesign the amplifier to lower gain. Then the gain will cross the 0-dB at low frequency and phase margin is increased.
In this way you don't wast current and probably the system will still work with e.g. 75-dB gain.
- Or take a look at the transistors M3/4 to push the second pole to higher frequencies.

Regards

I would go with Berti´s solution. If offset  is not a big concern, just reduce the input diff pair gm to lower the gain to get a better PM number.

Tosei

Input referred noise is reduced by increasing the input gm because the other noises like current sources become less effective.

I think the resistor reduces the effective gm of M3,4 to reduce the noise sources from M3,4 because M3,4 act like source degeneration.