hello,
i m trying to model in vhdl-ams low drop-out voltage regulator,
i m searching for existing model, but i don’t find ...  ::)
in some one know some ams existing model, that's will be fine

Chouba,

What do you need the LDO model for?  In your simulation testbench will the models of the load be drawing current from the LDO or are you just supplying a voltage?  

Don't go bananas modeling details like load regulation and line regulation if the output serves as the power supply to a sea of digital gates.

Will the model be used in a suite of full chip verification testcases?  If so, even if you need all the details (like load and line regulation) for a few testcases, you certainly do not need those details for the other 98% of testcases.

Or on the other hand, are you doing top-down design and plan to use a model of the LDO as an "executable spec" and designing the LDO schematic later?  In that case you need the model to behave as realistically as possible.

Cheers,

Bob P.
www.RPeruzzi.com