Hi

In case you are trying to simulate it, please see http://www.designers-guide.org/Forum/YaBB.pl?num=1204012103. It might shed some light on what you are looking for.

Tosei

Hi,

Typically, the offset of a well-designed comparator is dependent largely on the mismatch between the 2 input transistors.
Mostly, the threshold voltage mismatch of the 2 transistors gives you information about the offset directly.

You can get this data from your process doc. If the gain of the first stage (assuming multiple gain stages are present) is not
large enough (< 10 say), then the load devices in the first stage may also contribute. But for rough estimation, I would just
use the threshold voltage mismatch. It works for me. Hopefully, it works for you too.

Regards
Vivek