Dear all,

I would like to have a second opinion on a Mentor Graphics paper on simulating fractional-N PLL synthesizers.
In the paper "Efficient Simulation Techniques for Modulated Delta-Sigma Fractional-N Synthesizers" by Cyril Descleves (Mentor Graphics Corp), which can be download from their website, the simulation of a fractional-N PLL
is discussed.

In this paper, the FFT of the VCO tune voltage is shown, taken from a closed loop PLL simulation. Note that the FFT is plotted versus a linear frequency scale (Fs=Fref=26MHz). What can be seen nicely on this picture is the noise shaping from the delta sigma modulator. No problem so far.

I have than tried to recreate this simulation output (same reference frequency, same loop filter components etc.), but I observe a different FFT output. Namely, beyond the loop filter bandwidth, the VCO tune voltage is decreasing with 20dB/decade. This could/would be the loop filter kicking in, filtering off the sigma delta quantization noise. So, basically, I do not obtain the large 'horizontal' part in the graph.

Since I run these simulations using a FastSPICE simulator, I'm not 100% certain this is not a simulation accuracy issue.

If it is not, it would mean that the graphs in the Mentor Graphics paper are incorrect.

Any comments more than welcome.

Kind Regards

Peter

ps: please note that I'm not using Mentor tools to recreate this graph