Forum
Forum
Verilog-AMS
Analysis
Modeling
Design
Theory
Welcome, Guest. Please
Login
or
Register.
Please follow the Forum
guidelines
.
Jul 16
th
, 2024, 10:44am
Home
Help
Search
Login
Register
PM to admin
The Designer's Guide Community Forum
›
Modeling
›
Behavioral Models
› how to model polyphase filter
‹
Previous topic
|
Next topic
›
Pages: 1
how to model polyphase filter (Read 921 times)
Faisal
Community Member
Offline
Posts: 90
how to model polyphase filter
Mar 03
rd
, 2008, 1:42pm
Hi,
I am looking to make a behavioral model of the polyphase filter (along with the mismatch effects)
Back to top
IP Logged
Stefan
Senior Member
Offline
Posts: 124
Re: how to model polyphase filter
Reply #1 -
Mar 3
rd
, 2008, 2:35pm
So - what's the question or the problem ?
Back to top
IP Logged
jbdavid
Community Fellow
Offline
Posts: 378
Silicon Valley
Re: how to model polyphase filter
Reply #2 -
Apr 13
th
, 2008, 10:29pm
do the actual filter using electrical nets..
use ddt for the caps, (I = C dV/dt)
each cap and each resistor can have the mismatch added on using the $rdist_normal function
YOu can even, generate new mismatch values on a timer.
Back to top
jbdavid
Mixed Signal Design Verification
IP Logged
Stefan
Senior Member
Offline
Posts: 124
Re: how to model polyphase filter
Reply #3 -
Apr 13
th
, 2008, 11:22pm
You don't need to use electrical nets, you can also use signal-flow disciplines like wreal for them. This makes the whole simulation faster, but you'll need to use $dist_normal instead of $rdist...
Regards,
Stefan
Back to top
IP Logged
Pages: 1
‹
Previous topic
|
Next topic
›
Forum Jump »
» 10 most recent Posts
» 10 most recent Topics
Design
- RF Design
- Analog Design
- Mixed-Signal Design
- High-Speed I/O Design
- High-Power Design
- Mixed-Technology Design
Analog Verification
- Analog Functional Verification
- Analog Performance Verification
Measurements
- RF Measurements
- Phase Noise and Jitter Measurements
- Other Measurements
Modeling
- Semiconductor Devices
- Passive Devices
»» Behavioral Models
- Transmission Lines and Other Distributed Devices
Design Languages
- Verilog-AMS
- VHDL-AMS
Simulators
- Circuit Simulators
- RF Simulators
- AMS Simulators
- Timing Simulators
- System Simulators
- Logic Simulators
Other CAD Tools
- Entry Tools
- Physical Verification, Extraction and Analysis
- Unmet Needs in Analog CAD
General
- Tech Talk
- News
- Comments and Suggestions
- Opportunities
« Home
‹ Board
The Designer's Guide Community Forum
» Powered by
YaBB 2.2.2
!
YaBB
© 2000-2008. All Rights Reserved.
Copyright 2002-2024
Designer’s Guide Consulting, Inc.
Designer’s Guide
® is a registered trademark of
Designer’s Guide Consulting, Inc.
All rights reserved.
Send comments or questions to
editor@designers-guide.org
. Consider
submitting
a paper or model.