I am a newbie with NCSim.

I tried to elaborate a Verilog design with ncelab and this warning message was produced:

ncelab: *W,BIGWBS (<design_file.v>,1140|38): bit-select index truncation.

I tried "nchelp ncelab BIGWBS" and it gave the following info:

The index in a bit-select has a width greater than a machine word, which is typically 32 bits. Only 32 bits are used.
This truncation may result in undesired behavior.


Has Anyone come across this before?

Is it because of somthing wrong with my codes?

Is there any way to solve/get ride of/bypass this warning except using the "-NOWARN" OPTION?

Thanks

Thanks for the info.  :)