Hello, all

I read an application note @ the following link.
www.intersil.com/data/an/an051.pdf
I found a voltage level translator can be used to turn on and off Q3 and Q4 and was wondering how to implement that translator.
By the way, I also want to know exactly drains/sources of Q3 and Q4 in each phase because drains and sources are inverted in each clock and substrates need to be the most negative in every clok.
Thanks.