Hi Tosei,

I would tie it to the bulk of the main current mirror. By the way, the name "pseudo-cascode" is confusing. After all, you are simply extending the length
of the transistor by adding another element in series, just as you would use multiple elements in series with gates and bulks shorted if you wanted to make
an extremely long and narrow transistor, say 1/1000.

Regards
Vivek

Hi Tosei,

Leaving out the math for the moment, I would say that a current ratio of 2:1 is anyway not achieved that easily if the lengths are scaled as 1:2. This is because the simple, scalable, square-law model is anyway not applicable to most cases, unless you are using extremely long channel devices.

So you would need to do some tweaking regardless of the method you use. You would need to check but I think that the impact of body effect in the cascode transistor ought to be minimal. A larger VT also means that the drain voltage (for an NMOS mirror) can be lower than the gate by a larger amount before the transistor leaves the saturation region, to give a long-channel analogy. However, you will need to check with the particular mirror design you are using. In any case, the supply rejection of the mirror will be better when both devices share the same bulk node as the Gmb of the cascode will kick in to enhance the gain due to the cascode.

Regards
Vivek

Hi Tosei,

Good that you found the old link. I was going to post it myself. I almost forgot while writing the last post that you are speaking of "pseudo-cascodes" where both gates are tied together. Some of my previous post to you here is thus incorrect or irrelevant.

I think you must have figured out from the previous old discussions that you basically have only 1 transistor when you connect 2 in series and have the same gate and bulk. So, there is really no need to worry about body effect as it is not relevant.

When we speak of body effect, we are speaking of the source end of the channel and the V(G,S) needed to create inversion there, but in your "pseudo-cascode" connection, that source end is the lower transistor, which anyway has its source and bulk tied together. The "channel" of the pseudo-cascode extends from the source of the lower device to the drain of the higher one.

I don't quite understand what you mean when you speak of the difficulty in conciliating both approaches. Perhaps you can explain.

Regards
Vivek

Hi Tosei,

(A) Tying both bulks together
This reduces the 2 devices to 1 single transistor. Thus, you have a reference transistor with current I, and ratio (W/L) vs. a mirror transistor with length(W/2*L). This will give a ratio of 2:1. I don't see why this would not be the case provided you use relatively large devices to get around short-channel effects.

(B) Tying source-bulk together for top transistor
This changes the situation. I would say that you will not get 2:1 current ratio. Maybe you can run a simple simulation to see for yourself.

A good test would be to do a DC sweep on the reference current and see which mirror gives a more faithful 2:1 ratio. I bet it would be (A).

Regards
Vivek

Hi Tosei,

I cannot offer you an equation-based explanation. It is too dangerous, since the assumptions used may not hold. Let me try another explanation:

(A) will clearly have a current ratio of 2:1 if you are able to neglect short-channel effects (have long enough channels) and channel-length modulation, because essentially you have just 1 transistor.

(B) This is not the same scenario as (A). If A has 2:1 and this is different, then it cannot possibly be 2:1.

When you write the equations, you assume that one transistor is in saturation or linear region. I find this problematic, because you cannot really know this a priori, nor can you know the drain voltage Vd1 a priori (which amounts to the same thing).

Just to show that this assumption of regions of operation is problematic, let me outline 2 scenarios:

(A) You cannot directly assume that transistor 1 is in linear region and transistor 2 in saturation. If  Vd2 is large enough in relation to Vg-Vt, you may have no channel at all in transistor 2 and there may even be pinchoff in transistor 1. Conduction still occurs. After all, it also occurs despite pinchoff at the drain end in a transistor.

(B) Since bulk-source are tied together in transistor 2, this has a higher (Vgs-Vt). It is conceivable that neither transistor is in saturation when you do this.

If you really want to make a reality check, try running some sims with a LEVEL 0 SPICE model of a MOSFET where you can really get square-law behavior and other distractions are missing. I rest my case.

Regards
Vivek