Hyvonen
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Posts: 15
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Depending on the bias conditions and the oscillation amplitude of the VCO in question, drain-bulk voltage might not exceed VDD after all. Looking at the schematic, it seems that NMOS bulks are tied to their sources (triple-well process?), so bulk DC voltage is VDD-Vgs,nmos. If the oscillation amplitude is really high, gate-bulk/drain/source voltage may exceed breakdown limit, but otherwise this circuit might work fine.
Instead of looking at voltages as referenced to ground (or VSS/0V etc.), what really matters is what voltages (=potential differences) the transistor "sees." Look at the gate-drain, gate-bulk and gate-source voltages; if they are all below VDD, you're OK.
(Note that whenever one starts employing bulk bias tricks to extend operating voltage ranges, start-up should be planned in a way that the critical voltages are not exceeded at any point.)
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